1. Technical Field
Embodiments of the present disclosure relate to a semiconductor device that removes a phase error in multiphase signals. Particularly, embodiments of the present disclosure relate to a semiconductor device that compares inputted multiphase signals with each other, in order to control a delay amount of each phase signal, thereby removing a phase error in the multiphase signals.
2. Related Art
FIG. 1A is a block diagram of a conventional multiphase signal generator and FIG. 1B is a timing diagram illustrating an operation of the multiphase signal generator of FIG. 1A.
As illustrated in FIG. 1A, the conventional multiphase signal generator includes a multiphase signal generation circuit 10, a phase comparator 20, a charge pump 30, and a filter 40. The multiphase signal generation circuit 10 includes a plurality of variable delay sections 11 that delay an inputted clock signal Vp0, so that the multiphase signal generation circuit 10 can generate a plurality of multiphase signals, e.g., Vp1 to Vp5. The phase comparator 20 compares phases of the multiphase signal Vp5 outputted by the multiphase signal generation circuit 10 with the inputted clock signal Vp0. The charge pump 30 adjusts a level of an output voltage in response to a comparison result of the phase comparator 20. The filter 40 controls a delay amount of the multiphase signal generation circuit 10 according to the output voltage of the charge pump 30.
In FIG. 1A, among the inputted clock signal Vp0 and multiphase signals Vp1 to Vp4 output from the plurality of variable delay sections 11 of the multiphase signal generation circuit 10, two signals having neighboring phases preferably have a phase difference obtained by dividing one cycle of the inputted clock signal Vp0 into five equal parts. However, as illustrated in FIG. 1B, in the conventional multiphase signal generator, the inputted clock signal Vp0 and the outputted multiphase signal Vp5 are compared with each other, and the filter 40 stops controlling the delay amount of the multiphase signal generation circuit 10 when phases of the two signals Vp0 and Vp5 have no phase difference.
Accordingly, when a delay amount of each delay section 11 in the multiphase signal generation circuit 10 changes by a factor such as process variation, a phase difference between two signals having neighboring phases may not be equivalent to that of another two signals having neighboring phases. That is, a phase difference between two signals having neighboring phases, among the signals Vp0 to Vp4, may be different from a phase difference obtained by dividing one cycle of the inputted clock signal Vp0 into five equal parts.